1. Field of Invention
This invention relates generally to semiconductor memories and specifically to semiconductor memories having one or more defective cells.
2. Description of Related Art
Modern semiconductor memory devices such as, for instance, SRAM, DRAM, EEPROM, and Flash Memory, store millions of bits of information on a single chip. These memory devices require at least one transistor per memory cell, in addition to the thousands of transistors required for peripheral logic functions, e.g., row and column decoders, sense amps, and so on. Thus, even when manufactured using state of the art wafer fabrication technology, a one Megabyte semiconductor memory device may include hundreds or even thousands of defective cells. Additional memory cells may become defective during operation of such semiconductor memories. Although numerous well known redundancy techniques are available to repair defective memory cells, implementation of such techniques consumes considerable silicon area and is therefore typically impractical where die size is of primary concern.
The extent to which defective memory cells affect computer performance depends in part upon the particular application for which the semiconductor memory is used. For instance, since video data is relatively static, i.e., adjacent pixel information is often identical, the presence of one or two defective cells in a common row i.e., page, of memory has a minimal effect upon the resultant video image. However, where all bit information is vital, e.g., when storing encryption key information, the presence of even one defective cell can significantly degrade performance.
Application-Specific Integrated Circuits (ASIC) are well known and typically include an on-chip semiconductor memory. ASICs are used in a wide variety of applications ranging from cellular phones to dishwashers to DVD players and typically perform vital functions for their hosts, e.g., a DVD player. When some of the memory cells of an ASIC become defective during operation, the corresponding page of the memory becomes unusable. In some applications, a defective page may render the entire memory defective and, therefore, render the ASIC useless. Since, as described above, cell redundancy circuitry is often not feasible, there is a need to compensate for defective memory cells while sustaining normal ASIC operation, and without consuming additional silicon area.